Modern single chip digital systems employ multiple processors, but, for cost reasons, a single external memory or other shared resource. Present generation System On a Chip and Network On a Chip (SOC, NOC) memory architectures use arbitration allowing and limiting access to common resources in an attempt to meet the needs of multiple consuming elements. The basic method used today is physical arbitration that is fixed or programmable and in some cases adaptive.
In a physical priority scheme at each multiplexing junction where multiple requesting bus sources come together to access a single bus resource an arbiter picks the highest priority requesting source and gives it access to the resource. This system is referred to as physical because of the method it uses—each requesting source is assigned a priority, either statically (i.e. fixed), or programmable, at the junction and this is used to decide between multiple active requesting sources. A physical bus is assigned the priority irrespective of the originating source of the request, and only on the bus present at the point of arbitration.
Looking at the bus physical structure and all possible routes between sources of requests and resources, while it is possible to generate routes of higher importance than others, it is also possible to generate routes where the importance varies along the length of the route, which leads to the risk of priority inversion and, in consequence, to deadlocks. The usual solution is to use an arbitration algorithm like round-robin to avoid this problem at the cost of not being able to optimize the delays. This, in turn, forces the designer to implement additional redundancy in the application to cope with the wider delay variation which reduces efficiency.
An alternative solution tries to move the issues to the resource, here the requests are routed as fast as possible to the resource but not executed. At the resource the arbiter chooses the order in which the requests will be serviced then executes the request and responds back to the source of the request. This requires a complex bus architecture that allows pre-emption and expects that each junction or node in the bus fabric can retain outstanding requests. This method, although more complex, is still prone to the same hazards as the one previously described if the storage in the junction or nodes is full under high loads.